1. Field of the Invention
The present invention relates to complementary metal-oxide-semiconductor (CMOS) technology. More particularly, it relates to combining a compressively strained SiGe channel of a PMOSFET with a local tensile strained Si channel of an NMOSFET, such that a band gap narrowing of the CMOSFET and improving holes and electrons mobility of the PMOSFET and NMOSFET, respectively.
2. Description of the Related Art
The density of integrated circuits (IC) continues to increase and feature size thereof continues to scale down, improving the performance of IC devices and lowering manufacturing costs. Shorter channel length causes gate electrodes to lose channel controllability due to the short channel effect (SCE). This controllability problem can be solved by reducing the thickness of the gate dielectric layer (silicon dioxide), and this decreases the operating voltage and increases driving current. As a result, the leakage current is significantly increased with a direct tunneling effect, and the controllability issue still exists.
The physical thickness of high-k materials is much thicker than that of silicon dioxide under the same capacitance. With high-k materials serving as a gate dielectric layer, the electric filed in dielectric is lower under a same bias voltage, thereby decreasing the current leakage. High-k gate dielectrics are therefore considered to be a promising solution for replacing conventional silicon dioxide.
Semiconductor technology includes high-temperature processes, such as activation annealing after ion implantations. In the conventional art, poly-Si has been widely used as gate material due to its thermal budget and interface properties with silicon dioxide. When IC dimensions decrease, the poly-Si has issues of poly depletion and sheet resistance. In deep submicron CMOSFET technology, introduction of metal-gates has become a mainstream method for reducing the described problems.
To design a high speed CMOSFET with lower power loss, threshold voltages of PMOSFET and NMOSFET have to be oppositely symmetric. To obtain a tunable work function of metal gate in a CMOS, dual metal-gate electrodes or ion implantation to tune work function is applied. The former, however, is a complex process, and the latter is limited by solid solubility.
A method for reducing the channel effective band gap in a single workfunction metal gate, band gap offset of strained Si and strained SiGe channels are disclosed in IEEE EDL, vol. 25-6, pp. 402-404, entitled “Strained-Si-Strained-SiGe Dual-Channel Layer Structure as CMOS Substrate for Single Workfunction Metal-gate Technology”, published in June 2004. In this method, a compressively strained Si0.4Ge0.6 layer as a hole channel and a tensile strained Si layer as an electron channel are formed sequentially on a Si0.7Ge0.3 virtual substrate, wherein the Si layer of a PMOSFET is thicker than that of the NMOSFET to make sure that the reversion channel in the compressively strained SiGe layer. As shown in FIG. 1, tensile strained Si (region I), compressively strained Si0.4Ge0.6 (region II), relaxed Si0.7Ge0.3 buffer (region III), and bulk Si (region IV) are used as channels with different energy gaps. The tensile strained Si enhances electron mobility significantly in NMOSFET. However, the tensile strained Si cannot significantly improve the hole mobility in PMOSFET. Using compressively strained Si0.4Ge0.6 as a hole channel can enhance the operational speed of the PMOSFET. Therefore, the cited paper applies the Si0.4Ge0.6 and the tensile-strained Si as channels of the PMOSFET and the NMOSFET, respectively, such that the effective band gap is narrower than the bulk Si by 0.5 eV (from 1.1 eV to 0.6 eV). An ideal oppositely symmetrical threshold voltage of the PMOSFET and the NMOSFET can be obtained by a single metal-gate of 4.5 eV workfunction. This method requires a SiGe virtual substrate that leads increasing costs and the thickness of the ultra-thin Si cap layer overlying the PMOSFET is difficult to control.
Presently strained channel engineering mainly comprises global strain and local strain. Disadvantages of the global strain include high cost, low hole mobility, and high defect density in the SiGe virtue substrate. The disadvantage of the local strain is difficult in process control.
U.S. Pat. No. 6,784,507 discloses a structure of CMOSFET and BiCMOSFET, which includes a PMOSFET having a compressively strained SiGe channel, and an NMOSFET having a Si channel. A compressively strained SiGe channel is used for enhancing the hole mobility of the PMOSFET, but the electron mobility of the NMOSFET is not improved.
An improvement of mobility enhancement by strained channel CMOSFET with single workfunction metal-gate and a fabrication method is called for.